//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date        : Mon Nov 11 15:14:30 2019
//Host        : DESKTOP-EVCEGS1 running 64-bit major release  (build 9200)
//Command     : generate_target Add_4bit.bd
//Design      : Add_4bit
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "Add_4bit,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Add_4bit,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=4,numReposBlks=4,numNonXlnxBlks=4,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=4,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "Add_4bit.hwdef" *) 
module Add_4bit
   (A0,
    A1,
    A2,
    A3,
    B0,
    B1,
    B2,
    B3,
    CI,
    Y0,
    Y1,
    Y2,
    Y3,
    Y4);
  input A0;
  input A1;
  input A2;
  input A3;
  input B0;
  input B1;
  input B2;
  input B3;
  input CI;
  output Y0;
  output Y1;
  output Y2;
  output Y3;
  output Y4;

  wire A0_1;
  wire A1_1;
  wire A2_1;
  wire A3_1;
  wire Add_1bit_4_CO;
  wire Add_1bit_4_Y;
  wire Add_1bit_5_CO;
  wire Add_1bit_5_Y;
  wire Add_1bit_6_CO;
  wire Add_1bit_6_Y;
  wire Add_1bit_7_CO;
  wire Add_1bit_7_Y;
  wire B0_1;
  wire B1_1;
  wire B2_1;
  wire B3_1;
  wire CI_1;

  assign A0_1 = A0;
  assign A1_1 = A1;
  assign A2_1 = A2;
  assign A3_1 = A3;
  assign B0_1 = B0;
  assign B1_1 = B1;
  assign B2_1 = B2;
  assign B3_1 = B3;
  assign CI_1 = CI;
  assign Y0 = Add_1bit_4_Y;
  assign Y1 = Add_1bit_5_Y;
  assign Y2 = Add_1bit_6_Y;
  assign Y3 = Add_1bit_7_Y;
  assign Y4 = Add_1bit_7_CO;
  Add_4bit_Add_1bit_4_0 Add_1bit_4
       (.A(A0_1),
        .B(B0_1),
        .CI(CI_1),
        .CO(Add_1bit_4_CO),
        .Y(Add_1bit_4_Y));
  Add_4bit_Add_1bit_4_1 Add_1bit_5
       (.A(A1_1),
        .B(B1_1),
        .CI(Add_1bit_4_CO),
        .CO(Add_1bit_5_CO),
        .Y(Add_1bit_5_Y));
  Add_4bit_Add_1bit_5_0 Add_1bit_6
       (.A(A2_1),
        .B(B2_1),
        .CI(Add_1bit_5_CO),
        .CO(Add_1bit_6_CO),
        .Y(Add_1bit_6_Y));
  Add_4bit_Add_1bit_6_0 Add_1bit_7
       (.A(A3_1),
        .B(B3_1),
        .CI(Add_1bit_6_CO),
        .CO(Add_1bit_7_CO),
        .Y(Add_1bit_7_Y));
endmodule
